FIG. 1 is a circuit structural view of a power factor correction circuit disclosed in Japanese Patent Application No. 2000-37072. In the power factor correction circuit shown in FIG. 1, connected to both output terminals of a full-wave rectifying circuit B1, which rectifies an alternating current power-supply voltage of an alternating current power-supply Vac1, is a series circuit that is comprised of a booster reactor L1, a switch Q1 composed of a MOSFET, and a current detection resistor R. Connected across both terminals of the switch Q1 is a series circuit that is comprised of a diode D1 and a smoothing capacitor C1, and connected across the smoothing capacitor C1 is a load RL. The switch Q1 is PWM controlled by a control circuit 100 to be turned on and off.
The current detection resistor R detects an input current flowing through the full-wave rectifying circuit B1.
The control circuit 100 is comprised of an error amplifier 111, a multiplier 112, an error amplifier 113, an oscillator (OSC) 114 and a PWM comparator 116.
The error amplifier 111 has a “+” terminal applied with a reference voltage E1 and a “−” terminal applied with a voltage developed across the smoothing capacitor C1, upon which an error between a voltage of the smoothing capacitor C1 and the reference voltage E1 is amplified to generate an error voltage signal that is outputted to the multiplier 112. The multiplier 112 multiplies the error voltage signal delivered from the error amplifier 111 and a full-wave rectified voltage delivered from a positive-electrode terminal P1 of the full-wave rectifying circuit B1.
The error amplifier 113 has a “−” terminal applied with a voltage proportional to the input current detected by the current detection resistor R and a “+” terminal applied with the multiplied output voltage delivered from the multiplier 112, upon which an error between a voltage developed across the current detection resistor R and the multiplied output voltage is amplified to generate an error voltage signal that is outputted as a feedback signal FB to the PWM comparator 116.
The PWM comparator 116 has a “−” terminal applied with a ramp signal from the OSC 114 and a “+” terminal applied with the feedback signal FB from the error amplifier, generating a pulse signal for causing the switch Q1 to be turned on when a value of the feedback signal FB exceeds a value of the ramp signal and turned off when the value of the feedback signal FB is less than the value of the ramp signal. This pulse signal is applied to a gate of the switch Q1.
That is, the PWM comparator 116 outputs a duty pulse, depending on an error signal delivered from the error amplifier 113 between an output of the current detection resistor R and an output of the multiplier 112, to the switch Q1. The duty pulse is a pulse width control signal that continuously compensates a power factor in terms of variations in the alternating current power-supply voltage and a direct current load voltage for fixed cycles. With such a structure, an alternating current power-supply current waveform is so controlled as to align with an alternating current power-supply voltage waveform, remarkably improving the power factor.
Now, operation of the power factor correction circuit with such a structure is described with reference to a timing chart shown in FIG. 2. Also, FIG. 2 shows waveforms of a voltage Q1v developed across the switch Q1, a current Q1i flowing through the switch Q1, and a current D1i flowing through the diode D1.
First, as the switch Q1 is turned on at time t31, a current Q1i flows from the full-wave rectifying circuit B1 to the switch q1 via the booster reactor L1. This current linearly and progressively increases with time being elapsed to time t32. Also, during a time period between time t31 and time t32, the current D1i flowing through the diode D1 is at zero.
Next, at time t32, the switch Q1 shifts from the turned-on state to a turned-off state. In this moment, the voltage Q1v of the switch Q1 raises due to exciting energy induced in the booster reactor L1. Moreover, during a time period between time t32 and time t33, since the switch Q1 remains in the turned-off state, the current Q1i flowing through the switch Q1 remains zero. Also, during a time period between time t32 and time t33, the current D1i flows in a path expressed as L1→D1→C1 and electric power is supplied to the load RL.